1. Field of the Invention
The present invention relates to a memory circuit used in a field of data processing, and more specifically to a bit manipulation circuit capable of using one memory in common.
2. Description of Related Art
In microcomputers configured to use one memory in common, generally, a time sharing system is used in which one common memory is accessed (read or written) at different timings by a central processing unit (called a "CPU" hereinafter) and a peripheral function section including for example a timer and an interrupt controller. In this time sharing system, if the common memory is not accessed by one of the CPU and the peripheral function section, the other of the CPU and the peripheral function section can access the common memory. Conventionally, the common memory used in the time sharing system has been so constructed that 8 bits of data in the common memory are accessed as one unit by the CPU and the peripheral function section access. However, in the case that the memory is used as a flag or the like, the 8-bit data is often used in units of one bit. This is ordinarily called a "bit manipulation".
In the case of executing the bit manipulation, the 8-bit data to which the bit manipulation is to be executed is read out of the memory, and the read-out 8-bit data is supplied to a logic gate such as an AND gate or an OR gate so that an objective bit of the read-out 8-bit data is set or reset, and thereafter, the read-out 8-bit data is subjected to an arithmetic and logic operation. The read-out 8-bit data subjected to the arithmetic and logic operation is written back to the same location (address) of the memory as that of the memory from which the 8-bit data was read out. This sequential operation is called a "read-modify-write" operation.
In this "read-modify-write" operation, the peripheral function section performing the bit manipulation accesses to the memory when the data is read from the memory and when the data subjected to the arithmetic and logic operation is written to the memory, but does not access the memory when the arithmetic and logic operation is being performed for the read-out data.
For example, when the CPU performs the bit manipulation for data of the memory, there is possibility that during a period in which the CPU performs the arithmetic and logic operation for the read-out data, the peripheral function section rewrites the data stored in the location (address) of the memory as that of the memory from which the 8-bit data was read out by the CPU. In order to prevent this situation, the conventional microprocessor has included a flag bit for inhibiting the memory access of the peripheral function section during not only a memory access period of the CPU but also a period of the bit manipulation. This flag bit is called a "semaphore bit". This semaphore bit is also provided in association with the peripheral function section in order to prevent a similar situation when the peripheral function section performs the bit manipulation for dan of the memory.
Thus, in the conventional microcomputers, when the read-modify-write operation for the bit manipulation is performed by one of the CPU and the peripheral function section, the semaphore bit is activated to inhibit the memory access made by the other of the CPU and the peripheral function section, during the period in which the one of the CPU and the peripheral function section performs the arithmetic and logic operation for the read-out data. Therefore, a substantial time has been required for each one operation of the bit manipulation. In addition, since the memory can be accessed only after the semaphore bit is checked, the performance of the CPU resultantly lowers.